Verification and Validation of ITER Interlock System Fast Architecture According to IEC 61508 Standard

The ITER Interlock Control System (ICS) requires the application of IEC 61508 standard for all mission-critical (known as investment protection) control functions. Such functions must detect events integrated physical processes and distribute them to actuators with hard real-time constraints on order milliseconds or even microseconds. Systems able achieve these timing requirements are often bespoke FPGA-based solutions, which a well-known challenge processes. However, minimize variety components simplify procurement process an international supplier base, decided standardize use Commercial Off-The-Shelf (COTS) devices. COTS selected ICS was CompactRIO NI 9159 chassis (and several adapter I/O modules), provided by National Instruments (NI). This high-level language (LabVIEW-FPGA) associated development tools develop FPGA functionality. Therefore, it is necessary ensure required assurance that device sufficient quality, fit purpose, can be properly into protection loop level systematic capability during process. paper describes in detail method uses perform verification validation according recommendations, logic configuration generated LabVIEW-FPGA COTS, after compilation sources designed development.